In reply to Have_A_Doubt:
This question was addressed before
https://verificationacademy.com/forums/systemverilog/assigning-interface-net-type-signals-class
Quote:
1800-2012 14.3 Clocking block declaration
- A clockvar whose clocking_direction is inout shall behave as if it were two clockvars, one input and one output, having the same name and the same clocking_signal.
- Reading the value of such an inout clockvar shall be equivalent to reading the corresponding input clockvar.
- Writing to such an inout clockvar shall be equivalent to writing to the corresponding output clockvar.
Code example provided,
Also, see
https://verificationacademy.com/forums/systemverilog/clocking-block-interface