In reply to Verif_Learner_SG:
See (2) - EDA Playground
That seems to satisfy your requirement.
I added the pass1 and err1 signals used in the action block to help in the debugging and display. I also modified the range for sig3 for simplicity.
**($rose(sig1), v=data_load) ##1 (data_load!=v[=>1] intersect sig2[->1]) |->
##[1:5] sig3;
**
// Code your testbench here
// or browse Examples
module top;
bit clk,reset;
bit sig1,sig2,sig3;
int data_load=0, pass1, pass2, err1, err2;
always #5 clk=!clk;
// If new sig1 then data_load will be stable starting from the next clock
// until sig2. At sig2 data_load is changed in value and in the next cycle sig3==1
/*property p_with_sig2;
int v;
@(posedge clk) disable iff(reset)
($rose(sig1), v=data_load) |-> ##1 first_match(data_load==v[*1:$] ##1 sig2)
##0 data_load !=v ##1 sig3;
endproperty
ap_with_sig2: assert property (p_with_sig2);*/
// if data_load changes between Sig1 and Sig2 posedges,
// then Sig3 must get asserted within let's say 1 to 10 clocks
property p_with_no_sig2;
int v;
@(posedge clk) disable iff(reset)
//($rose(sig1), v=data_load) ##1 (data_load!=v[->1] intersect sig2[->1]) |->
// shOULD BE [=1]
($rose(sig1), v=data_load) ##1 (data_load!=v[=1] intersect sig2[->1]) |->
##[1:5] sig3;
endproperty
ap_with_no_sig2: assert property (p_with_no_sig2) pass1=pass1+1; else err1=err1+1;
initial begin
$dumpfile("dump.vcd");
$dumpvars(0);
#200 $finish;
end
initial begin
fork
#7 sig1<=1;
#23 sig2<=1;
#18 data_load<=10;
// #26 sig3<=1;
join
end
endmodule