In reply to ben@SystemVerilog.us:
Hello Ben,
Here, I am expecting if data_load changed between sig1 and sig2, If Sig3 is not asserted, It is an error.
Actually, I have different checkers to check, whether sig2 is asserted or not after sig1 is asserted.
I added your code in eda-playground and found that even though data_load changed, sig2 asserted but even though sign3 was not asserted, It is not throwing an error.
Thank you for your time, I am sure it is quite challenging to match the spec while reading my spec description.
Let me try to see while changing your property or other suggested implementation to achieve my check.