Need clarification on UVM Objection mechanism

UVM
1

Hi
I am learning UVM concepts and have a query on objection mechanism. In example codes from the internet, i see the objection is raised only on the test class instead of raising in its verification components. Here is a example from cookbook:

Test

task reset_phase( uvm_phase phase);
phase.raise_objection( this );
reset_seq.start( m_sequencer );
phase.drop_objection( this );
endtask

In this case, what is the difference in raising objection in reset_seq and raising object in test?
Is it required to raise objection in both test and sequence?

Regards

2

If all your sequences block until they are done, then raise/drop objections in the test is sufficient and other calls to raise/drop objection inside the sequence are redundant overhead. The objection mechanism is an expensive operation so it is best to reduce the amount of calls to raise or lower. Also, it makes your sequence less reusable if you want to use it in a passive mode and then you don’t want an objection to ending the test.

3

In reply to dave_59:

Thank you dave for your valuable reply.
Now i understand the usage of objection mechanism.

Regards