Need a help on below assertion writing

SystemVerilog
, ,
6

In reply to Raghunandan Reddy:

In above code some typo error is there where i forget to mention the continuous repeat operator(*) which ben had rectified in his reply.

 // I can conclude my code should be as below	
property check_1;
		$rose(s1) |=> first_match($stable(s2) ##[*0:$] ##1 $rose(s3),$display($stime(),"PASS"));
endproperty

	CHECK_1: assert property (@(posedge clk) check_1) $display("Assertion pass 1");