My wall clock simulation time for different speeds(250 MHz and 500 Mhz) is coming almost same

SystemVerilog
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1

Hi,
I am trying to send 1000 packets each of 20 bytes in two different speeds i.e, 250 MHz and 500. I am expecting that simulation time should become half of what it is taking in 250 Mhz. But it is coming almost same. I have checked both the clocks are working correctly.

Please suggest some ways to correct this issue.

2

In reply to vi_shal:

What time is is taking and why do you expect the simulation to run faster?

3

Hi Dave,
Thanks for responding.

I am kind of checking the performance of my model. So, when I increase the clk frequency the send and receive should complete faster.

Simulation time for both the cases is coming around 3 mins 20 secs.

Though I can see the difference between the timestamps on reception of 1000th packet, for 250MHz its printing around 5.5 Lac nano secs and for 500 MHz its printing around 2.8 Lac nano secs (working according to my expectation). But not sure why simulation time is same.

I am not sure whether this difference should also reflect in real time simulation. Please correct me If I am expecting anything wrong here.

4

In reply to vi_shal:

Simulation walk clock doesn’t care about the speed of a single clock—it’s the same amount of work simulating the same number of clock edges. The period of simulation time between each clock edge is only kept for reporting and visualization.

But if the amount of work a simulation changes because of a changes because of a different clock speed (the simulation test period remains the same, or there are multiple clocks) then the CPU effort will change.

5

Hi Dave,
Thanks for the clarification.
But if this is the case then how will I get to know that whether My model is working correctly with the DUT, as there is no real time difference on increasing transmission speed.

Thanks…