My randomization is failing

UVM
,
1

for plusargs
i define the variable plusargs into top and set using config_db and geting into the sequence and constraning that variable into transaction class and redomizig the into sequence but my randomization is failing

if($value$plusargs("variable",variable_min))
$display("variable_min=%d",variable_min);
if($value$plusargs("variable",variable_max))
$display("variable_max=%d",variable_max);
uvm_config_db#(byte)::set(null,"*","variable",variable_min);
uvm_config_db#(byte)::set(null,"*","variable",variable_max);

into seq class

byte variable_min,variable_max;
task body()
if(!uvm_config_db#(byte)::get(null,"","variable",variable_min)
 `uvm_fatal(get_type_name,$sformatf("did not received variable_min"))
if(!uvm_config_db#(byte)::get(null,"","variable",variable_min)
 `uvm_fatal(get_type_name,$sformatf("did not received variable_min"))

tans tx; //tansaction handle
and giving it memory
if(1)
assert(tx.randomize() with {variable_min==variable_min;});
else
assert(tx.randomize() with {variable_max==variable_max;});
into tx class
constrant c{addr>variabe_min;addr<variable_max;}

2

In reply to Ashishkumar072:

Even though you didn’t fully provide the constraint , I believe it should be like

 constraint c { 
       addr > variable_min;
       addr < variable_max;
 }

So if that’s the case, both “variable_min” and “variable_max” are getting the same value which fails the constraint.
You should update the “field_name” ( currently its “variable”) for variable_min and variable_max . It shouldn’t be same for both variables.

3

In reply to Someshg:

yes i change but still same isuue i am getiing.

4

In reply to Ashishkumar072:

Could you please paste your code on EDAPlayground.com.

5

In reply to Ashishkumar072:
Can you paste your full code ?

Also under tx.randomize() variable_max is not randomized to variable_max value since it’s under else part. So it could have taken lesser value than variable_min . So providing the full code will help better.

6

The problem could be using same name. Please use this keyword to differentiate which class they belong to.

assert(tx.randomize() with {variable_min==this.variable_min;});

7

In reply to jyoveda:

The problem could be using same name. Please use this keyword to differentiate which class they belong to.
assert(tx.randomize() with {variable_min==this.variable_min;});

That is incorrect. Use:

assert(tx.randomize() with {variable_min==local::variable_min;});
8

In reply to dave_59:

module tb;
//variable decleration
bit [7:0] axi_awaddr_up_master_min;
bit [7:0] axi_awaddr_down_master_min;
bit [7:0] axi_awaddr_up_master_max;
bit [7:0] axi_awaddr_down_master_max;

//value plusargs
if($value$plusargs(“axi_awaddr_up_master_min”, axi_awaddr_up_master_min))
        $display(“axi_awaddr_up_master_min=%0d”, axi_awaddr_up_master_min);
if($value$plusargs(“axi_awaddr_down_master_min”, axi_awaddr_down_master_min))
        $display(“axi_awaddr_down_master_min=%0d”, axi_awaddr_down_master_min);
if($value$plusargs(“axi_awaddr_up_master_max”, axi_awaddr_up_master_max))
        $display(“axi_awaddr_up_master_max=%0d”, axi_awaddr_up_master_max);
if($value$plusargs(“axi_awaddr_down_master_max”, axi_awaddr_down_master_max))
        $display(“axi_awaddr_down_master_max=%0d”, axi_awaddr_down_master_max);
//configuration set
Uvm_config_db#(bit[7:0])::set(null,”*”,”axi_awaddr_up_master_min”,axi_awaddr_up_master_min);
Uvm_config_db#(bit [7:0])::set(null,”*”,”axi_awaddr_down_master_min”,axi_awaddr_down_master_min);
Uvm_config_db#(bit [7:0])::set(null,”*”,”axi_awaddr_up_master_max”,axi_awaddr_up_master_max);
Uvm_config_db#(bit [7:0])::set(null,”*”,”axi_awaddr_down_master_max”,axi_awaddr_down_master_max);
  endmodule

//tansaction class
bit [7:0] axi_awaddr_up_master_min;
bit [7:0] axi_awaddr_down_master_min;
bit [7:0] axi_awaddr_up_master_max;
bit [7:0] axi_awaddr_down_master_max;
rand bit [127:0] addr;

 constraint  c{addr>axi_awaddr_up_master_min; addr>axi_awaddr_down_master_min; addr<axi_awaddr_up_master_max; addr<axi_awaddr_down_master_max;}
endclass


//seq class
bit [7:0] local_axi_awaddr_up_master_min;
bit [7:0] local_axi_awaddr_down_master_min;
bit [7:0] local_axi_awaddr_up_master_max;
bit [7:0] local_axi_awaddr_down_master_max;
task body();
if (!uvm_config_db# (bit [7:0])::get(null,” ”,”axi_awaddr_up_master_min”local_axi_awaddr_up_master_min))
  `uvm_fatel (get_type_name,$sformatf(“did not axi_awaddr_up_master_min”))
if (!uvm_config_db# (bit [7:0])::get(null,” ”,”axi_awaddr_down_master_min”local_axi_awaddr_down_master_min))
  `uvm_fatel (get_type_name,$sformatf(“did not axi_awaddr_down_master_min”))
if (!uvm_config_db# (bit [7:0])::get(null,” ”,”axi_awaddr_up_master_max”local_axi_awaddr_up_master_max))
  `uvm_fatel (get_type_name,$sformatf(“did not axi_awaddr_up_master_max”))
if (!uvm_config_db# (bit [7:0])::get(null,” ”,”axi_awaddr_down_master_max”local_axi_awaddr_down_master_max))
  `uvm_fatel (get_type_name,$sformatf(“did not axi_awaddr_down_master_max”))

    Assert(tx.randomizae() with {axi_awaddr_up_master_min==local_axi_awaddr_up_master_min; axi_awaddr_down_master_min==local_axi_awaddr_down_master_min; axi_awaddr_up_master_max==local_axi_awaddr_up_master_max; axi_awaddr_down_master_max==local_axi_awaddr_down_master_max;});
Endtask

//problem is inline constraint is falling//

9

In reply to Ashishkumar072:
apology for late reply ,I tried that way you have suggested but still facing same the same issue.

if possible can we meet
thanks regard
ashish kumar

10

In reply to chr_sue:

module tb;
//variable decleration
bit [7:0] axi_awaddr_up_master_min;
bit [7:0] axi_awaddr_down_master_min;
bit [7:0] axi_awaddr_up_master_max;
bit [7:0] axi_awaddr_down_master_max;

//value plusargs
if($value$plusargs(“axi_awaddr_up_master_min”, axi_awaddr_up_master_min))
$display(“axi_awaddr_up_master_min=%0d”, axi_awaddr_up_master_min);
if($value$plusargs(“axi_awaddr_down_master_min”, axi_awaddr_down_master_min))
$display(“axi_awaddr_down_master_min=%0d”, axi_awaddr_down_master_min);
if($value$plusargs(“axi_awaddr_up_master_max”, axi_awaddr_up_master_max))
$display(“axi_awaddr_up_master_max=%0d”, axi_awaddr_up_master_max);
if($value$plusargs(“axi_awaddr_down_master_max”, axi_awaddr_down_master_max))
$display(“axi_awaddr_down_master_max=%0d”, axi_awaddr_down_master_max);
//configuration set
Uvm_config_db#(bit[7:0])::set(null,””,”axi_awaddr_up_master_min”,axi_awaddr_up_master_min);
Uvm_config_db#(bit [7:0])::set(null,””,”axi_awaddr_down_master_min”,axi_awaddr_down_master_min);
Uvm_config_db#(bit [7:0])::set(null,””,”axi_awaddr_up_master_max”,axi_awaddr_up_master_max);
Uvm_config_db#(bit [7:0])::set(null,””,”axi_awaddr_down_master_max”,axi_awaddr_down_master_max);
endmodule

//tansaction class
bit [7:0] axi_awaddr_up_master_min;
bit [7:0] axi_awaddr_down_master_min;
bit [7:0] axi_awaddr_up_master_max;
bit [7:0] axi_awaddr_down_master_max;
rand bit [127:0] addr;

constraint c{addr>axi_awaddr_up_master_min; addr>axi_awaddr_down_master_min; addr<axi_awaddr_up_master_max; addr<axi_awaddr_down_master_max;}
endclass

//seq class
bit [7:0] local_axi_awaddr_up_master_min;
bit [7:0] local_axi_awaddr_down_master_min;
bit [7:0] local_axi_awaddr_up_master_max;
bit [7:0] local_axi_awaddr_down_master_max;
task body();
if (!uvm_config_db# (bit [7:0])::get(null,” ”,”axi_awaddr_up_master_min”local_axi_awaddr_up_master_min))
uvm_fatel (get_type_name,$sformatf(“did not axi_awaddr_up_master_min”)) if (!uvm_config_db# (bit [7:0])::get(null,” ”,”axi_awaddr_down_master_min”local_axi_awaddr_down_master_min)) uvm_fatel (get_type_name,$sformatf(“did not axi_awaddr_down_master_min”))
if (!uvm_config_db# (bit [7:0])::get(null,” ”,”axi_awaddr_up_master_max”local_axi_awaddr_up_master_max))
uvm_fatel (get_type_name,$sformatf(“did not axi_awaddr_up_master_max”)) if (!uvm_config_db# (bit [7:0])::get(null,” ”,”axi_awaddr_down_master_max”local_axi_awaddr_down_master_max)) uvm_fatel (get_type_name,$sformatf(“did not axi_awaddr_down_master_max”))

Assert(tx.randomizae() with {axi_awaddr_up_master_min==local_axi_awaddr_up_master_min; axi_awaddr_down_master_min==local_axi_awaddr_down_master_min; axi_awaddr_up_master_max==local_axi_awaddr_up_master_max; axi_awaddr_down_master_max==local_axi_awaddr_down_master_max;});

endtask

11

okay

12

because constraint dose not work on non rand declared value.

13

In reply to ashish_saroj:

i am not randoming that variable i use to controll the rand variable using plusargs.

14

In reply to Ashishkumar072:

//tansaction class
bit [7:0] axi_awaddr_up_master_min;
bit [7:0] axi_awaddr_down_master_min;
bit [7:0] axi_awaddr_up_master_max;
bit [7:0] axi_awaddr_down_master_max;
rand bit [127:0] addr;-------------this variable we are randomizing

15

that will be not possible if you put value from $plus$valueargs in rand variable it will not work properly