Mutuality constraint

SystemVerilog
, ,
4

In reply to gotlibhaim:
You would get better help from people if you showed your code as a complete self-contained example.

module top;
typedef enum {A,B,C,D} p_e;
class c;
   rand p_e pA[2], pB[2];
   constraint c1 { foreach(pA[i]) if(pA[i] == C)  pB[i] dist{C:= 1, D:= 1}; }
   constraint c2 { foreach(pB[i]) if(pB[i] == C)  pA[i] dist{C:= 1, D:= 1}; }
endclass: c
c h=new;
  initial repeat(50) begin
     assert(h.randomize());
     $display("%p %p", h.pA[0], h.pB[0]);
  end
endmodule

Your constraint certainly does allow the result B,C. there is no dist constraint when portA_Type[i] = B