Is QuestaSim 10.0b capable of handling multithreaded UVM TB for implementation on multi-cores of my system. If yes then how that can be achieved? I came to know about Questa MC2 which deals well with multithreading on multi-core SOCs but is that same possible using my Questa as i dont have access with Questa MC2 but want to incorporate the multithreading concept using my UVM testbench?
The answer is no. The reason for this is that the SystemVerilog engine is designed to be single-threaded to ensure proper functionality and there is no way to handle execution across multiple processor cores.
With Questa MC2, the DUT will be partitioned into separate simulation blocks with the simulator handling all the cross-partition communication automatically. Since the DUT typically occupies the majority of the simulation processing, partitioning allows these threads to operate independently and reduce overall simulation time. Even with MC2, the SystemVerilog part of the testbench will remain in a single thread.