I have a design and UVM verification environment for this design. The design has registers and the VENV also has a register model. APB protocol is used to access the register of design.(There are APB UVCs in the VENV) However, an additional interface was added to the design for accessing registers of design. I have implemented the UVCs of the protocol. I already have a register model and it is connected to the APB UVCs. I need to verify access to the registers with the new interface. I want to use the register model but I guess it doesn’t make sense to add the same register model for the new interface. So, I thought how about wrapper UVC like a prei_uvc. The register model will be connected to the env of peri_uvc and the APB UVCs and the new interface UVCs will be operated according to the type of sequence item.
Before implementation, I want to get feedback on my thoughts. Is it reasonable and possible? And, if you have a good idea to use multiple interfaces with one register model, please share the idea.
Thanks.