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SystemVerilog
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2

In reply to Satputesb:
Two solutions, one for the static delay and another one for the dynamic delay.
The sva_delay_repeat_range_pkg is available in my signature below.


// Compile  sva_delay_repeat_range_pkg.sv before the module 
module m; 
  import sva_delay_repeat_range_pkg::*; // for use in dynamic delaya
  typedef enum {A, B} st_e;
  st_e st; 
  bit clk, rst, q; 
  int delay=5;
  // Way one is timeout through STATIC time p. And another is if we see rise in signal q.
  let p=4; 
  ap_stAB_static: assert property(@ (posedge clk) 
    disable iff(rst)
    st==A |-> (##p st==8) or  ($rose(q)[->1] ##1 st==B));   

 // If the delay is dynamic, use the package
 /* Application:  $rose(a)  |-> q_dynamic_delay(d1) ##0 my_sequence;
    ap_dyn_delay: assert property(@ (posedge clk) 
       $rose(a) |-> q_dynamic_delay(d1) ##0 my_sequence);  */ 
   ap_stAB_dynamic: assert property(@ (posedge clk) 
       disable iff(rst)
       st==A |-> (q_dynamic_delay(delay) ##0 st==8) or  ($rose(q)[->1] ##1 st==B));      

endmodule : m

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
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    Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
  3. Papers:

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