Multiple clocks in an assertion

SystemVerilog
,
2

In reply to rrkk66418:

Yes, there is a standard on that, and it is limited to ##0 or ##1.
sv1800’2017 16.13.1 Multiclocked sequences
Multiclocked sequences are built by concatenating singly clocked subsequences using the single-delay concatenation operator ##1 or the zero-delay concatenation operator ##0. The single delay indicated by ##1 is understood to be from the end point of the first sequence, which occurs at a tick of the first clock, to the nearest strictly subsequent tick of the second clock, where the second sequence begins. The zero delay indicated by ##0 is understood to be from the end point of the first sequence, which occurs at a tick of the first clock, to the nearest possibly overlapping tick of the second clock, where the second sequence begins.

On your other question:


@(posedge slow_clk_A) $changed(A)|-> ##1 @(posedge fast_clk_B) $changed(B)
// is same as 
@(posedge slow_clk_A) $changed(A)|-> 
             @(posedge slow_clk_A) 1 ##1 @(posedge fast_clk_B) $changed(B)
// The sampling is at the nearest strictly subsequent tick of the second clock,

// vs
@(posedge slow_clk_A) $changed(A)|-> @(posedge fast_clk_B) ##1 $changed(B)
the nearest possibly overlapping tick of the second clock, where the second sequence begins.

See the explanation with an example that I provided in my SVA book
http://systemverilog.us/vf/Multiclock.pdf

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  2. Free books: Component Design by Example https://rb.gy/9tcbhl
    Real Chip Design and Verification Using Verilog and VHDL($3) Amazon.com
  3. Papers: