Multidimensional array of interface

SystemVerilog
,
1

I am trying to have a multidimensional array of interface, is it leggal to have a multidimensional array of interface.

example code :
interface intfa();
logic a;
endinterface
module test;
reg clk=0;
intfa int_a();
intfa int_aa3;
intfa int_aa1[3:0]2:0; // is it leggal ?
endmodule

In Questa it is working but when i am using it with cadence it is not working.

2

In reply to vadivelan014:

This is legal if you follow the formal syntax

module_instantiation ::= module_identifier [ parameter_value_assignment ] hierarchical_instance { , hierarchical_instance };
hierarchical_instance ::= name_of_instance ( [ list_of_port_connections ] )
name_of_instance ::= instance_identifier { unpacked_dimension }

Where curly braces mean “this can exist 0 or more times” so you can have 0, 1 or multiple ‘unpacked_dimension’

You’ll need to talk to the individual vendors themselves about specific tool support for this.