In reply to ben@SystemVerilog.us:
Thank you ,here i seen issue
@(posedge clk2) en[->1]##1 v==fifo_lvl2;
##1 delay is considering @(posedge clk1),i am expecting @(posedge clk2).
clk1 = clk2/2 (here i can use ##2 instead of ##1 to fix above problem - But i don’t want to do work around - is there any way of waiting for ##1 on clk2?)
Thank you.