In reply to gani:
bit[3:0]fifo_lvl,fifo_lvl2;
bit valid, en;
//Collect the value fifo_lvl, when valid is high @clk1.
//when en = 1@(clk2) & after one clk cycle of (@clk2) Compare with fifo_lvl == fifo_lvl2.
property p_fifo;
bit[3:0] v;
@(posedge clk1) (valid, v=fifo_lvl) |->
@(posedge clk2) en[->1] ##1 v==fifo_lvl2;
endproperty
ap_fifo: assert property(p_fifo);
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115