Hi
I am in the process of learning questasim. I am trying to compile the code from Getting Started with UVM: A Beginner’s Guide. I am getting the following error while compiling the following code. My hirearchy goes like this
interface
dut(pipe)
my_seq_pkg includes
data_pkt
pipe_seq_library
end my_seq_pkg
my_pkg includes
pipe_sequencer
pipe_driver
pipe_monitor
pipe_agent
pipe_scoreboard
pipe_coverage
pip_env
end pkg
top includes my_pkg and my_sequences
when i compile the following code, i get the following error
vlog uvmbook.sv
** Note: (vlog-2286) Using implicit +incdir+C:/questasim_10.0b/uvm-1.0p1/…/verilog_src/uvm-1.0p1/src from import uvm_pkg
– Compiling interface pipe_if
– Compiling module pipe
– Compiling package my_sequences
– Importing package mtiUvm.uvm_pkg (uvm-1.0p1 Built-in)
** Warning: uvmbook.sv(108): (vlog-2269) Unterminated string literal continues onto next line 108.
** Warning: uvmbook.sv(114): (vlog-2643) Unterminated string literal continues onto next line.
– Compiling package my_pkg
– Importing package my_sequences
** Error: uvmbook.sv(266): near “#”: syntax error, unexpected ‘#’, expecting IDENTIFIER or ‘=’
C:/questasim_10.0b/win32/vlog failed.
===========================================================================================
class pipe_monitor extends uvm_monitor;
`uvm_component_utils(pipe_monitor)
uvm_anlaysis_port #(data_packet) item_collected_port;
data_packet data_collected;
data_packet data_clone;
virtual pipe_if vif;
string monitor_intf;
int num_pkts;
function new(string name, uvm_componet parent);
super.new(name,parent);
endfunction: new
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db #(string)::get(this, "", "monitor_intf", monitor_intf))
`uvm_fatal("NOSTRING", {"Need interface name for: ",get_full_name(),".monitor_intf"})
`uvm_info(get_full_name(), $sformatf("INTERFACE USED = %0s", monitor_intf),UVM_LOW)
if(!uvm_config_db #(virtual pipe_if)::get(this, "", "monitor_intf", vif))
`uvm_fatal("NOVIF", {"Virtual interace must be set for: ",get_full_name(),".vif"})
item_collected_port = new("item_collected_port",this);
data_collected = data_packet::type_id::create("data_collected");
data_clone = data_packet::type_id::create("data_clone");
`uvm_info(get_full_name(), "Build stage complete.", UVM_LOW)
endfunction: build_phase
virtual task run_phase(uvm_phase phase);
collect_data();
endtask: run_phase
virtual task collect_data();
forever begin
wait (vif.enable)
data_collected.cf = vif.cf;
data_collected.data_in0 = vif.data_in0;
data_collected.data_in1 = vif.data_in1;
repeat(3) @(posedge vif.clk);
data_collected.data_in0 = vif.data_in0;
data_collected.data_in1 = vif.data_in1;
$cast(data_clone, data_collected.clone());
item_collected_port.write(data_clone);
num_pkts++;
end
endtask:collect_data
virtual function void report_phase(uvm_phase phase);
`uvm_info(get_type_name(), $sformatf("REPORT: COLLECTED PACKETS = %0d", num_pkts),UVM_LOW)
endfunction: report_phase
endclass: pipe_monitor