Module parameterized with class type

SystemVerilog
1

To my initial surprise it to be possible to use a class as type for a module parameter?

E.g.

module my_param_mod #(parameter type VAR_TYPE = integer)
    (input clk);
    initial begin
        automatic VAR_TYPE x=new;
        x.x=5;
        x.y=6;
        for(int i=0;i<10;i++) begin
            $display("x=%p",x);
        end
    end
endmodule

class myc;
    int x;
    int y;
endclass;

bit clk=0;
my_param_mod #(.VAR_TYPE(myc)) m1(.clk(clk));

I thought the module and class based parts of SV were pretty separate?
Are there any limitations to this kind of mixing of classes and modules?

2

In reply to NiLu:

Section 6.20.3 Type parameters of the IEEE 1800-2012 standard which describes type parameters doesn’t mention any such limitation. This is probably something the vendor hasn’t implemented.

3

There have never been any such limitations in the SV standard. You can even pass class handles through ports of a module.

The key limitation with classes is where you are allowed reference a class member or method - only from procedural code.

So that means you can use a continuous assignment to assign one class variable to another class variable, but you cant continuously assign a class member to another member.

module top #(type VAR_TYPE);
VAR_TYPE a,b;
assign x = y; // legal
assign a.x = b.x; // illegal
endmodule

Note: you do not need the parameter keyword in the parameter list, and you should not assign the parameter a default if you want to require the user to provide an override. You will get much more meaningful error messages if the user fails to provide an override than leaving the type as integer.

4

In reply to dave_59:

Thanks! Very useful feedback.