Hey all!
I’m wondering how I can modify register rights during runtime? just like set_access for uvm_reg field.
In reply to abdelaali_21:
I believe the register rights you are referring to are part of uvm_reg_map. You would need to create a different map for different register rights.
In reply to dave_59:
Her Dave,
Thank you for your reply.
What I want to do is to modify register rights from RO to RW during runtime. I honeslty didn’t understand what you meant, Please, can you tell me how can I create a different map for the register? is there a way to handle this in .ralf?
In reply to abdelaali_21:
You can change the access rights of individual fields at runtime with set_access.
The only other access rights are with uvm_reg_map. You can have multiple maps for the same registers.
Maybe you need to explain better the reason why you want to change the register rights at runtime, and not use RW to begin with.
You’ll need to discuss this with your RALF tool provider how you might do this.
In reply to abdelaali_21:
I’m trying to understand what the value is to modify the access rights of registers during the simulation.
The register description is a document which is valid for the design (RTL) and the testbench. Modifying access rights only in the testbench might result in a desaster.
Hi all and thank you for your reactivity !
| You can have multiple maps for the same registers.
How can I do this ?
| Maybe you need to explain better the reason why you want to change the register rights at runtime.
the reason is when a bit of another register(let’s call it cntrl_reg) is set, some fields of some registers change their access (from RO to RW), this field access changing worked for the registers that have at least 1 RW field (so the register in .sv is created with RW rights) but some registers only contain RO fields (so the register in .sv is generated with RO rights) and the field access changing doesn’t work for the fields of this register).
| and not use RW to begin with
with only RO fields in register, the register is automatically generated with RO rights.
| I’m trying to understand what the value is to modify the access rights of registers during the simulation.
Some of my RTL register change their acees during runtime. and I need to verify this by doing the same in testbench so I can make sure register .mirror works fine.