In reply to chr_sue:
Hi chr_sue,
The figure is not previewed as I entered, sorry.
To describe my env.:
1- My DUT has two interfaces: Custom and SPI.
2- I am accessing the DUT registers via custom interface. I developed a register model (RAL) to access DUT registers via frontdoor access. I am using a custom VIP for this interface.
3- My DUT is accessing a CAN-IC via SPI interface and writing/reading CAN_IC registers. Here my DUT is SPI master. I am using SPI Questa VIP (VIP from Mentor) for SPI interface.
4- I need a model to mimic CAN-IC registers that my DUT can reach. Here SPI VIP will use this model.
For your questions:
1- Yes. I already developed a register model for them for access via custom i/f.
2- UVM Register Abstraction Layer model.
3- Verification IP
4- QVIP (Questa Verification IP)
5- Yes, SPI and custom i/f.
6- No, through custom i/f.
Thanks.