Modeling registers of a chip

UVM
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In reply to rdemirci:

I’m getting confused viewing your figure.
I try to ask a few questions to get some more specific information.

  1. Your DUT has regsietres inside you want to access from testbench?
  2. What kind of register model do you have? a UVM model or something else.
  3. Whatis VIP?
  4. SPI QVIP is a UVM VIP.
  5. Dou you have additional interfaces?
  6. Are you accessing your DUT-internal registers through the SPI interface?

Would be grear if you could answer my questions.