In reply to MICRO_91:
The intention is to check for sequence : ( a ##1 b ) ##[min:max] ( c ##1 d )
I address this with examples is my paper
http://systemverilog.us/vf/ap_a2bnext3cnextd_range.sv
ap_a2bnext3cnextd_range : assert property(@(posedge clk) $rose(a) ##2 b|-> ##[1:3] c ##1 d);
also in http://systemverilog.us/vf/a_range_one.sv
ap_a1to5b_then_3c : assert property(@(posedge clk) $rose(a) ##[1:5] b |-> ##3 c);
Regarding your code in
@( posedge clk ) a ##1 b |-> ##0( 1, dynamic_delay_range( min , max ) ) ;
Delays or wait statements in match item task calls are not supported by some tools.
This is most likely because the tool vendor implemented the task call in the Observed region rather than the Reactive region.
In any case, your task dynamic_delay_range does not consider the sequence that follows it.
On your Q2, you are correct.
Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.
or Cohen_Links_to_papers_books - Google Docs
Getting started with verification with SystemVerilog