In reply to manoj_k86:
When I do it, I get:
$ verror 2643
Model Technology ModelSim SE verror 10.3 Extended Help Utility 2014.01 Jan 6 2014
verror 2643
Message # 2643:
A string literal shall be contained in a single line
unless the new line is immediately preceded by a (backslash).
In this case, the backslash and the newline are ignored.
There is no predefined limit to the length of a string literal.
[DOC: IEEE Std 1800-2012 Verilog LRM - 5.9 String literals]