Mixing types and operators in SystemVerilog

SystemVerilog
, ,
1

Hello,

I have a basic question about mixing datatypes and operators in SV, probably there is a section in the LRM but I’m not sure which could it be

Let’s say you have


module test();
  const int x = 10;
  const int y = 10;
  const real f= 0.95;
  int z;
  initial begin
    z = (x*f)/y;
    $display("x =%0d, y = %0d, f = %0f, z = %0d", x, y, f, z);
  end
endmodule

This outputs

KERNEL: x =10, y = 10, f = 0.950000, z = 1

I was expecting to be computed something like this
1- (xf) = 100.95 = 9.5 => int’(9.5) = 9
2- z = 9/10 = 0

Probably I’m missing something very basic here not necessarily about SV (general programming), any hint on which section of the LRM covers this is really appreciated.

2

In reply to rgarcia07:

According to Section 11.3.1 Operators with real operands in the 1800-2017 LRM, the result of any arithmetic operation with a real operand is a real. So the result of x*f is a real value 9.5. And the result of that real value divided by 10 is 0.95. That real result gets implicitly cast back to an int by rounding to 1(Section 6.12.2 Conversion).

3

In reply to dave_59:

Many thanks Dave