Mixing analogue (real types) and digital (logic and tri)

SystemVerilog
,
1

this is my first post to this forum so hello everybody: I work as a consultant RTL designer and verification, mostly in Verilog but vhdl is also ok.

I am porting a Verilog AMS model into system Verilog. Most of the job is to replace wire/reg with logic and define real port in the module declaration then removing wreal from the module body

so far so good

now my question is how to istantiate the top module of my analogue IP into the the digital top. This module has both logic and real port now so I wonder how to connect real port to the top mofile wires / logic without offending the simulator. currently I got type mismatch errors when doing this

Some comments
1- I cannot / do not want to modify the digital top (I like to keep the same netlist all over the flow

then a couple of solutions
2- should I let a vams model of the analogue top and use wreal herein to connect ‘real’ ports of the sub modules?
3- shouldn’t specify real types on the port declaration of the modules letting the compiler /elaborate derive the type by itself

I like solution nr.3, still I’d like to make sure it is correct

I also cannot connect modules with input and output ports of type ‘real’ using ‘real’ wires so I am more and more confused

Please show me the right / most convenient methodology for this

thanks much in advance

2

My knowledge in this area is limited, but I believe you should look at the interconnect feature of SystemVerilog. This is what lets the compiler derive the type of the port by what it is connected to.

Also, wreal is not part of the SystemVerilog standard, but some vendors support it under the appropriate switches. Check your documentation.

3

In reply to dave_59:

hello dave thank you very much. using nettype seems to selve the problem. Below a test case I assembled to show this up

// ncvlog -sgq 4g -sv -work worklib test_port.sv
// ncelab -sgq 4g -top worklib.digi_top:module
package netsPkg;
nettype real realNet;
endpackage: netsPkg

module digi_top(
input wire a, b,
output wire z
);
ana_top the_anatop (.a(a), .b(b), .z(z));
endmodule: digi_top

import netsPkg::*;
module ana_top(
input realNet a, b,
output realNet z
);
real ztmp;
real zout;
ana1 the_ana1(.ai(a), .bi(b), .z(ztmp));
ana2 the_ana2(.ai(ztmp), .bi(b), .z(z));
assign z=zout;
endmodule: ana_top

module ana1(
input real ai, bi,
output real z
);
assign z = ai**bi;
endmodule: ana1

module ana2(
input real ai, bi,
output real z
);
assign z = ai+bi;
endmodule:ana2