Mirror method not working : uvm_reg

UVM
1

Hi all,
I am using the Register model for the first time and dont know how to solve this Problem.
The Problem is reading the Status Register,
in my scoreboard I have this code:
task check_status();
while(1) begin
@(oterr)
if (oterr) reg_model.dig_top_pads.SUMSTAT.predict(8’h26);
end
endtask

and 100us after oterr happens I send a mirror in the sequence:
cfg.reg_model.dig_top_pads.SUMSTAT.mirror(status,UVM_CHECK);

but the uvm_err is generated:
the mirror value is updated but the read value from DUT is not matching and is all Zeros. however I can see that the collected Transaction from Monitor in correct:

UVM_ERROR /opt/questasim_10.1a/questasim/verilog_src/uvm-1.1/src/reg/uvm_reg.svh(2894) @ 1122707000: reporter [RegModel] Register “regmodel.dig_top_pads.SUMSTAT” value read from DUT (0x0000000000000000) does not match mirrored value (0x0000000000000026)

I appreciate any comment.
regards,

2

In reply to mohammed:

Hi Mohammed,
Have you get solution for this issue.
Please share with us if you have.

Thanks,
Raja.A

3

In reply to mohammed:

Could you please explain what is oterr and what you are doing with this. Why do you execute a predict command? Are you using explicit prediction?

4

Hi Mohammed,
Thanks for the reply.
I have fixed the issue by reset the register_model.
Now the mirror is working fine

Thanks,
Raja.A