In reply to S.P.Rajkumar.V:
I’m talking about Section 33. Configuring the contents of a design of the 1800-2012 LRM. This is actually a Verilog-2001 construct. Unfortunately, I haven’t been able to find any examples with any more detail than what is already in the LRM; Config is so heavily used by the UVM that it is hindering my search.
As far as tool flows are concerned, this requires a multi-step flow. This is where you compile modules into a separate design libraries, and compiling into each library requires a separate step, and then another step to elaborate the design for simulation. You will need to look in your tools User Manual for Verilog compilation flows, but you should contact your vendor for more specific help.