In reply to dave_59:
Hi Dave,
Can you help understand more about this?
“You may want to look at Verilog configurations using the config construct”.
Is verilog configuration a way to implement the multiple modules (default/limited functionality/dummy etc) concept you specified above?
Or, is this config construct approach a completely different one?
A pointer to a paper/example would be of help to understand this completely.
Currently, to implement the multiple module concept we use different compile time switches based on which we select different files in the filelist?
Thanks,
Rajkumar.