You may want to look at Verilog configurations using the config construct. You can use different definitions of the same module and choose a specific definition for a particular instance. You can also choose a specific definition for all instances (same as if there is only one instance) of a module. You may use your tool’s library mechanism as well by compiling different definitions into separate libraries, and then selecting the library you want to use for a particular test.
In any of the cases above, you still need to create empty module definitions, but you will not have to modify the existing RTL source code.