In reply to Wanglj:
Hello Wanglj,
I have forced clock and other signals before, but I have not got a change to notice how the other module instances got impacted because of this. Right now, I don’t have access to Questa to try this.
You are saying that forcing top.dut.i1.a1.clk is effecting top.dut.i1.a2.clk as well? Correct?
It can happen if your RTL is something like below, as all the instances clocks(i1.a1.clk, i1.a2.clk) are directly connected to the top clock (i1.clk) during instantiation. So, forcing i1.a1.clk would force i1.clk and inturn forces i1.a2.clk.
Hope that’s your case and as per my analysis thats the correct behavior.
module i1 (clk, in, out);
input clk;
…
…
…
wire in_a, in_b;
…
a1 a1(.clk(clk), in(in_a),…);
a2 a2(.clk(clk), in(in_b),…);
…
endmodule