In reply to S.P.Rajkumar.V:
Hi S.P.Rajkumar.V,
I have tried your method both in verilog and GUI, both cases show that forcing clock in one module will affect clock in the other module. Can you tell me which tool you are using, I am using Questasim.
In reply to S.P.Rajkumar.V:
Hi S.P.Rajkumar.V,
I have tried your method both in verilog and GUI, both cases show that forcing clock in one module will affect clock in the other module. Can you tell me which tool you are using, I am using Questasim.