Memory multi mapping in uvm_reg_map

UVM
1

Hi
Is there a way to map one uvm_mem to one uvm_reg_map a few times with different addresses?
(meaning: that the same phisical address in the memory is mapped once for addressA and again for addressB)

the straight forward way doesn’t work.
<code lang=“systemverilog” linenumbers=“normal” start=“43” fancy="7>
reg_map_1.add_mem( uvm_mem_1, 32’h0000_0000, “RW”);
reg_map_1.add_mem( uvm_mem_1, 32’h00FF_0000, “RW”);

it raises an error that the memory is already mapped to this map

" UVM_ERROR @ 0: reporter [RegModel] Memory ‘uvm_mem_1’ has already been added to map ‘reg_map_1’ "

Thanks

2

You can follow the example given by examples/simple/registers/models/aliasing, or you could simply create two map instances, supplying a different base address when creating them. Although separate instances, they use non-overlapping address ranges. If you keep your register sequences abstract as they should be, there shouldn’t be any references to specific maps unless you want writes/reads to occur over a specific address region, in which case the easiest way to do that is to refer to a different map object when calling write/read or to set the default map in parent block.

Reg block build():

uvm_reg_map map_a, map_b
  map_a = create_map("map_a",0,4,UVM_LITTLE_ENDIAN);
  map_b = create_map("map_b",0,'hFF_0000,UVM_LITTLE_ENDIAN);
  foreach (<list of regs in block>) begin
    map_a.add_reg(<reg handle>,<reg offset>,<rights>);
    map_b.add_reg(<reg handle>,<reg offset>,<rights>);
  end
  default_map = map_a;

Note that, with the above, the rights and offsets of each register in each map can be the same or different. Very flexible. The maps’ base addresses are already different (see create_map), so individual reg offsets can be identical.

In the env, you would configure both maps with the same sequencer/adapter, assuming the same bus is being used.

model.map_a.set_sequencer(agent.sequencer,bus_adapter);
  model.map_b.set_sequencer(agent.sequencer,bus_adapter);

A register sequence can then be executed using either map. If a map is not specified, the default_map for the reg model is used.

uvm_reg_map map; // map to use for this seq; set from outside
                   // if null, reg model uses the default
  task body();
    model.regA.write(status,'h33, .map(map), .parent(this));
    ...
  endtask

For explicit prediction, memories are not involved, but registers are. You’ll have to subtype the predictor to search two maps instead of the top-level reg model when looking for the reg that is mapped to the address seen on the bus.

3

In reply to Adam:

Hi Adam,

I am implementing the similar approach as per your suggestion.

Could also explain how to implement th explicit prediction part . “For explicit prediction, memories are not involved, but registers are. You’ll have to subtype the predictor to search two maps instead of the top-level reg model when looking for the reg that is mapped to the address seen on the bus”