Memory Frontdoor Reads and Writes are not transferred through predictor

UVM
,
1

I implemented the register model with memories and started running the memory tests. I’m seeing an issue where the memory test is able to send front door reads and writes but not able to collect the reads and writes. Looking at the adapter and predictor. It looks like it will only process register front door accesses. How do I get memory front door access to the register model to allow the memory test to use the values?
Here is my adapter code:
class BDA_RM_Adapter extends uvm_reg_adapter;
//Register object class
`uvm_object_utils(BDA_RM_Adapter);

function new(string name = “bda_rm_adapter”);
super.new(name);
// Does the protocol the Agent is modeling support byte enables?
// 0 = NO
// 1 = YES
supports_byte_enable = 0;

// Does the Agent's Driver provide separate response sequence items?
// i.e. Does the driver call seq_item_port.put()
// and do the sequences call get_response()?
// 0 = NO
// 1 = YES
provides_responses = 0;

endfunction

virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
BDA_QSPI_Seq_Item bda_tr = BDA_QSPI_Seq_Item::type_id::create(“bda_tr”);
SPI_Seq_Item_Base bda_tr_clone;
//Bad programming model that requires configuring seq_item to be routed through bus2reg adapter
//no docuemtnation pointing this out.
if(rw.kind == UVM_READ) begin
bda_tr.qcmdId = BDA_QSPI_Seq_Item::LocalRead;
bda_tr.rw = 1’b0;
end
else
begin
bda_tr.qcmdId = BDA_QSPI_Seq_Item::LocalWrite;
bda_tr.rw = 1’b1;
end

bda_tr.addr = {rw.addr[11:0]};
bda_tr.data = {rw.data[7:0]};
	bda_tr.cmd_packet();
	bda_tr.trans_cnt++;
	bda_tr_clone = bda_tr;
return bda_tr_clone; 
endfunction:reg2bus

virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);
	BDA_QSPI_Seq_Item bda_tr;
if (!$cast(bda_tr, bus_item)) begin
  `uvm_fatal("ADAPTER_WRONG_TR_TYPE","Provided sequence_item is not of the correct type")
  return;
end

	if(bda_tr.rw)
		begin
			rw.kind = UVM_WRITE;
		rw.addr = bda_tr.addr;
  		rw.data = {<<8{bda_tr.data[0]}};
  		rw.data = {<<8{rw.data}};
		end
	else
		begin
			rw.kind = UVM_READ;
		rw.addr = bda_tr.addr;
  		rw.data = {<<8{bda_tr.data[0]}};
  		rw.data = {<<8{rw.data}};
		end

rw.status = UVM_IS_OK;

endfunction:bus2reg

endclass:BDA_RM_Adapter