Maximum characters in a single line for System Verilog file in Questasim

Hi All,

Can any one help me ?

I am getting a compile time error while compiling an SV file and the compilation stops at 106th character of the line. Questa is not compiling this line beyond 106th character. Is it because Questasim restricts maximum no of characters on a single line for better readability?

I am currently using Questasim 10.4

Thanks,
Nishit

Questa and most other simulators can certainly handle line lengths over 106 characters. Code generated by macros and other utilities typically generate lines longer than that.

Without seeing your source code, I can’t tell you what the problem might be. But in any case this is not a tool specific forum and you should contact your vendor directly for support.