In reply to khaledma85:
This is interesting to me because I just had a discussion with a professor at UC Irvine who teaches SystemVerilog about the lack of verification topics covered for computer engineering students. Even my own son (who just graduated from Harvey Mudd, a leading engineering school in the US), barely had time in his curriculum to get through a SystemVerilog design course.
I think the problem is not limited to computer engineering. Students need to be taught design and verification concepts together for any engineering discipline, and that could be a whole course in itself. Its about a process that begins gathering requirements, creating a specification, and following that through to an end product that meets those original requirements. The classic tree/tire swing comic illustrates this brilliantly.
So trying to cram your curriculum into single course looking for practical examples seems impractical to me.