Magic square on system verilog

SystemVerilog
3

In reply to dave_59:

Hi Dave,

I modified the code, but i dont see rows 2 and 3 is equal to 15.

// Code your design here

class magicsquare;
  
  rand bit [7:0] a [0:2][0:2];
  rand bit [7:0] b [0:2][0:2];
  
  int i,j,k;
  
  constraint c1 {foreach (a[i,j]) 
    
  if (i==0)  {a.sum() with (int'(item)) ==8'd15; } }
      
      constraint c2 {foreach (a[i,j])
    
        if (i==1){ a.sum() with (int'(item)) == 8'd15 ;}}
      
    
      
   //   constraint c2 {foreach (a[i,j]) 
    
     //   if (i==0) {a.sum() with (int'(item)) ==8'd15; } }
  
  function void display ();
                 $display ("The value of array is %p",a);
                    
  endfunction
  
endclass

module test;
  magicsquare m1;
  
  
  initial begin
    m1=new();
    m1.randomize();
    m1.display();
    
  end
  
endmodule

Expected output:

2   7   6
  9   5   1
  4   3   8