Macro `ID is undefined

SystemVerilog
,
1

Hello,
I have two modules (two separate .v files) where the top module has a `define as shown in snippet below:

`define ID 32’h0000_0033
module top (
…
input clk,
input rstn,
endmodule

In a sub module, the macro `ID is used as shown in the snippet below:
module reg (
input clk,
…
);

logic [4:0] status;
logic [31:0] reg[0:2];

parameter ABC_ID = `ID;
…
casez (addr[6:0])
7’b000_0001: rdata = ABC_ID;

When I compile with vlog, I get the following error:
** Error: …/…/rtl/ctrl.v(37): (vlog-2163) Macro `ID is undefined.

I have the following in my compile .f file:
+incdir+…/…/rtl/

…/…/rtl/top.v
…/…/rtl/reg.v

Regards,
Mark

2

Since this is Verilog, you’ll need to put your define macro in a header file (.vh) and then include that file when you need that macro.

3

In reply to markylew:

Macro definitions do not exist outside their compilation unit. The SystemVerilog standard gives tools the ability to implement compilation units in various ways. Please look at the LRM section on compilation units, and your tools user manual for how it deals with single and multiple file compilation units.