I am guessing the behavior you want is for “data” (bit?) to go high, stay high for 3 cycles, and then go low. If so you want to check the whole sequence not just the end case.
You don’t have to call $rose, or posedge clock in the sequence declaration; it’s step delays already reference the clock from the @(posedge clk) code. ##1, etc, are inferred clock cycles.
I haven’t mastered assertion writing, so anyone feel free to verify the following line, but I think you want something more like:
$rose(data) |=> data[*3] ##1 !data