Loop to randomize RAL fields across multiple registers

SystemVerilog
1

Hi all — quick question about reducing repetitive RAL code.

I have two register objects, iplr0 and iplr1. Their fields are declared like this:

  • iplr0 contains:
rand uvm_reg_field irq0_prio;
rand uvm_reg_field irq1_prio;
...
rand uvm_reg_field irq7_prio;
  • iplr1 contains:
rand uvm_reg_field irq8_prio;
rand uvm_reg_field irq9_prio;
...
rand uvm_reg_field irq15_prio;

My goal is to randomize each IRQ priority so every field value is <= 3. Right now I do this manually:

void'(ral.iplr0.randomize() with {
  irq0_prio.value <= 3;
  irq1_prio.value <= 3;
  ...
  irq7_prio.value <= 3;
});
ral.iplr0.write(status, ral.iplr0.get());
ral.iplr0.update(status);

void'(ral.iplr1.randomize() with {
  irq8_prio.value <= 3;
  irq9_prio.value <= 3;
  ...
  irq15_prio.value <= 3;
});
ral.iplr1.write(status, ral.iplr1.get());
ral.iplr1.update(status);

This is verbose and error-prone. Can I do this with a single loop (or macro/helper) that iterates register index iplr0..iplr1 and fields irq0_prio..irq15_prio, sets each field to a value <= 3, and then writes/updates the registers? Any compact examples (using get_field_by_name, get_fields, macros, or small helper tasks) would be much appreciated.

Thanks!