Thank you Dave for your reply. Clock frequency is 250MHz.
I used various values for the registers and in the last check I had 255 bit instead of 32 for time_in (i.e. reg [255:0] time_in [N-1:0] ,where N = 5). Now putting the first delay to 255’d20000000000 gave me a 400 second delay. I used smaller values too such as 32’d200000000 which reduces the delay but i still do not get different delays in each if statement.