In reply to Amirros:
The problem is both i_dut.a and i_dut.b are wires driven by the dut module instance output ports a and b. Port a is being driven a continuous assignment from the variable ‘a’ which has the value 1’bx. That overrides any value assigned through the clocking block. You can fix that by assigning ‘a’ to 1’bz, or changing it back to a wire