Logic vs wire in black box port list

In reply to dave_59:

Hi Dave,
Thanks a lot. I actually read this section of the LRM today and figured that my previous assumption of the type of ‘a’ was wrong.
I still fail to understand how come that the ‘x’ on ‘a’ sticks for all the simulation time even tough that reset is de asserted and do_reset is called (‘b’ is initialized properly).