In reply to Amirros:
It’s slight more complicated than just logic versus wire. It is really net versus variable. The value of a net is the resolution function of all the drivers (continuous assignments) connected to the net. A wire is a kind of net that resolves to a Z when there are no active drivers on the wire. A variable is a storage element whose value is procedurally assigned. Prior to the first procedural assignment, the default value of a variable depends on the variable’s type. logic is a 4-state data type and its default initial value is X.
SystemVerilog has a lot of (too many IMHO) implicit declaration conventions. Here is what your black-box dut declaration looks like explicitly :
module dut (input wire logic clk,
input wire logic reset_n,
output var logic a, // a is variable
output wire logic b); // b is net
endmodule
You might want to look at sections 23.2.2.3 Rules for determining port kind, data type, and direction and 23.3.3 Port connection rules in the IEEE 1800-2017 SystemVerilog LRM.