Is the variable declaration inside generate ( logic data ) valid. Will the generated properties use a single data variable or will it create multiple variables(data). Please see the below code
generate for (genvar i=0;i<=WIDTH-1;i=i+1)
begin
property d_no_glitch;
logic data;
@(d[i])
(data = !d[i]) |=>
@(posedge clk)
(d[i] == data);
endproperty : d_no_glitch
a_doublesync_glitch:assert property(d_no_glitch);
In reply to vishnu_intel:
This should work fine (unless I am missing something). Do you see any issue? Just to be sure - with generate, your properties and assertions will be replicated N number of times with each a separate memory footprint. The “data” that you have is a local variable inside that property and gets dynamically allocated during various threads per-assertion.
BTW - I recommend you use named generate block.
Regards
Srini
www.verifworks.com