Logic keyword

SystemVerilog
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1

Please explain the sentence "A logic variable cannot be driven by multiple structural drivers " with a coded example

2

In reply to krishna_:

3

In reply to dave_59:
Hi Dave ,
Thank you so much for the reply.
After reading the blog, I understood that a logic varibale can’t be driven with a continous and procedural statement at a time which is Ex3. (Please correct me if I am wrong)
Below are the few examples I tried. Please explain me why the display is 10 in Ex2 and error in Ex1
Replacing logic with wire in Ex1 is also giving me the same error. Please explain me why.
Ex1:

module dut;  
   logic  [7:0] x;  
   assign x = 5;  
   assign x = 10;  
   initial $display("%0d",x);  
endmodule

Output: complie time error
(vlog-7045) ‘x’ is driven by more than one continuous assignment.
Ex2:

module dut;  
   logic [7:0] x;  
   initial x = 5;  
   initial x = 10;  
   initial $display("%0d",x);  
endmodule

Output: 10
Ex3:

module dut;  
   logic [7:0] x;  
   initial x = 5;  
   assign x = 10;  
   initial $display("%0d",x);  
endmodule

Output: complilation error
(vlog-12003) Variable ‘x’ written by continuous and procedural assignments.

4

In reply to krishna_:
You are allowed to make as many procedural assignment to the same variable as you want. Last write “wins”. Ex2 has two procedural assignments in two different processes in a race at time 0. Tools could display 5 or 10. Note that synthesis tools may impose further resitrctions by only allowing procedural assignments from a single process.