Logic implication on properties

SystemVerilog
1

Hi,

i know that some simulators support logic implication (‘->’) in properties and other not.

wonder if according LRM 1800-2009 it must be supported.

Thanks,
Nadav

2

The logical operator ‘->’ was added in the 1800-2009 LRM as a general purpose Boolean operator (not just for properties), and may not yet be supported in all simulators. Contact your vendor directly and request it.