Lock_model issue of uvm_ral

santosh_dv · March 18, 2020, 6:18pm

Hi,all
I am trying to write to dut register using uvm ral front door access ,when i am done with initial build of ral model , i am calling lock_model of uvm _reg_block to lock register model , it is not coming out of lock_model function of uvm_reg_block,below i have attached part of code here.
but it is not coming out of lock_model function(it is not returning from lock_model function).

Can anyone please tell me what is the issue here?

Thanks in advance.

`ifndef ping_pong_register;
`define ping_pong_register;
//---------------register field -------------------//
class ping_pong_register extends uvm_reg;
	rand uvm_reg_field ping_pong_reg_field;      
	
	`uvm_object_utils(ping_pong_register)

	function new(string name = "ping_pong_register");
      super.new(name, 32'd192, build_coverage(UVM_NO_COVERAGE));
	endfunction: new

  // Build all register field objects
  virtual function void build();
    
     `uvm_info(get_full_name(),"INSIDE ping_pong_register  starting of BUILD function",UVM_LOW)
    this.ping_pong_reg_field    = uvm_reg_field::type_id::create("ping_pong_reg_field",,   get_full_name());
   

    // configure(parent, size, lsb_pos, access, volatile, reset, has_reset, is_rand, individually_accessible); 
    this.ping_pong_reg_field.configure(this, 32'd192, 0, "WO", 1, 1'h0, 0, 0, 0);
     `uvm_info(get_full_name(),"INSIDE ping_pong_register starting of BUILD function",UVM_LOW)
  endfunction
endclass 

`endif

//-------------------register block----------------//

`ifndef ral_sys_eon;
`define ral_sys_eon;

class ral_sys_eon extends uvm_reg_block;
	rand ping_pong_register    pi_po_reg;       // RO
	

	`uvm_object_utils(ral_sys_eon)

	function new(string name = "ral_sys_eon");
		super.new(name, build_coverage(UVM_NO_COVERAGE));
	endfunction

  virtual function void build();
    `uvm_info(get_full_name(),"INSIDE ral_sys_eon  starting of BUILD function",UVM_LOW)
    this.default_map = create_map("", 0, 1, UVM_LITTLE_ENDIAN, 0);
    //3rd orgument in create_map indicates bus width of 1 byte
    this.pi_po_reg = ping_pong_register::type_id::create("pi_po_reg",,get_full_name());
    this.pi_po_reg.configure(this, null, "");
    this.pi_po_reg.build();
    //this.default_map.add_reg(this.ctrl, `UVM_REG_ADDR_WIDTH'h0, "RW", 0);
    this.default_map.add_reg(this.pi_po_reg,'h3f, "RO", 0);
    
    lock_model();

    `uvm_info(get_full_name(),"INSIDE ral_sys_eon  ending of BUILD function",UVM_LOW)
   
  endfunction 
endclass 
`endif

//------------------------------top environment in which i have instatiated uvm_ral environment----------------------------//

class eon_env extends uvm_env;
	 `uvm_component_utils(eon_env)
 spi_agent	s_agent_h;
 reg_env   reg_env_h;
 eon_scoreboard          eon_sb_h;
 spi_coverage			spi_covg_h;
        
        
function new(string name = "eon_env",uvm_component parent);
super.new(name,parent);
endfunction


	//***********build phase*****************//
	
    function void build_phase(uvm_phase phase);
      super.build_phase(phase);
      
      `uvm_info(get_full_name(),"INSIDE EON ENV starting of BUILD PHASE",UVM_LOW)

	// creating the handles 
	         
      s_agent_h = spi_agent :: type_id::create("s_agent_h",this);
      eon_sb_h = eon_scoreboard::type_id::create("eon_sb_h",this);
      spi_covg_h=spi_coverage::type_id::create("spi_covg_h",this);
      reg_env_h=reg_env::type_id::create("reg_env_h",this);
      
      `uvm_info(get_full_name(),"INSIDE EON ENV ending of BUILD PHASE",UVM_LOW) 
   
    endfunction

	function void connect_phase(uvm_phase phase);
		super.connect_phase(phase);
      
      `uvm_info(get_full_name(),"INSIDE EON ENV starting of CONNECT PHASE",UVM_LOW)

	// connecting the monitor and scoreboard
	 
      s_agent_h.spi_mon.spi_ap_h.connect(eon_sb_h.spi_fifo.analysis_export);
      s_agent_h.spi_mon.spi_ap_h.connect(spi_covg_h.analysis_export);
      s_agent_h.spi_mon.spi_ap_h.connect (reg_env_h.m_spi2reg_predictor.bus_in);
      reg_env_h.m_ral_model.default_map.set_sequencer(s_agent_h.spi_seqr, reg_env_h.m_reg2spi);

      `uvm_info(get_full_name(),"INSIDE EON ENV ending of connect PHASE",UVM_LOW)
    endfunction


endclass

//---------------RAL adapter ------------------//



class reg2spi_adapter extends uvm_reg_adapter;
 
  `uvm_object_utils (reg2spi_adapter)

spi_txn pkt;
  
  function new (string name = "reg2spi_adapter");
      super.new (name);
   endfunction

   virtual function uvm_sequence_item reg2bus (const ref uvm_reg_bus_op rw);
       pkt = spi_txn::type_id::create ("pkt");
     
     `uvm_info(get_type_name(),"reg to bus call inside adapter starting  ",UVM_MEDIUM)
//      pkt.set_sequencer (this.tmp_seqr);
     pkt.cmd_type = (rw.kind == UVM_WRITE) ? spi_txn::spi_txn_cmd_type_e'(1): spi_txn::spi_txn_cmd_type_e'(0);
      pkt.addr  = rw.addr;
     
    // pkt.data=new[4];
     pkt.data[0]  = rw.data[7:0];
     pkt.data[1]  = rw.data[15:8];
     pkt.data[2]  = rw.data[23:16];
     pkt.data[3]  = rw.data[31:24];
     
     `uvm_info(get_type_name(),$psprintf("packet is %s",pkt.sprint()),UVM_MEDIUM)
      
     `uvm_info(get_type_name(),"reg to bus call inside adapter ending  ",UVM_MEDIUM)
       
      `uvm_info ("adapter", $sformatf ("reg2bus addr=0x%0h data=0x%0h kind=%s", pkt.addr, pkt.data, rw.kind.name), UVM_DEBUG) 
      return pkt; 
   endfunction

   virtual function void bus2reg (uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);
      spi_txn pkt;
     
      
     `uvm_info(get_type_name()," bus2reg call inside adapter starting  ",UVM_MEDIUM)
     
     `uvm_info(get_type_name(),"bus_to_reg_call inside adapter ",UVM_MEDIUM)
      if (! $cast (pkt, bus_item)) begin
        `uvm_fatal ("reg2spi_adapter", "Failed to cast bus_item to pkt")
      end
   
      rw.kind = pkt.cmd_type== spi_txn::spi_txn_cmd_type_e'(1)? UVM_WRITE : UVM_READ;
      rw.addr = pkt.addr;
     
     
     rw.data[7:0] = pkt.data[0];
     rw.data[15:8] = pkt.data[1];
     rw.data[23:16] = pkt.data[2];
     rw.data[31:24] = pkt.data[3];
    
      
     `uvm_info(get_type_name()," bus2reg call inside adapter ending  ",UVM_MEDIUM)
       
      `uvm_info ("adapter", $sformatf("bus2reg : addr=0x%0h data=0x%0h kind=%s status=%s", rw.addr, rw.data, rw.kind.name(), rw.status.name()), UVM_DEBUG)
   endfunction
endclass


//-----------------test class -------------------//


`ifndef eon_ral_ping_pong_wr_test;
`define eon_ral_ping_pong_wr_test;

class eon_ral_ping_pong_wr_test extends base_test;
  
  

//----------FACTORY REGISTRATION----------------

  `uvm_component_utils(eon_ral_ping_pong_wr_test)

ral_sys_eon ral_sys_eon_h;
  


//-------------CONSTRUCTOR----------------------- 

  function new(string name="eon_ral_ping_pong_wr_test", uvm_component parent);

    super.new(name,parent);

  endfunction


  function void build_phase(uvm_phase phase);

    super.build_phase(phase);
  
    `uvm_info(get_full_name(),"BUILD PHASE - BASE TEST",UVM_LOW)
  
   

  endfunction
  
   function void connect_phase(uvm_phase phase);
    super.connect_phase(phase);
   this.ral_sys_eon_h=env_h.reg_env_h.m_ral_model;
  endfunction
  
    
   virtual function void end_of_elaboration_phase(uvm_phase phase);
    uvm_phase run_phase = uvm_run_phase::get();
     run_phase.phase_done.set_drain_time(this, 300ns);
  endfunction
  
  
  virtual task main_phase(uvm_phase phase);
     // ral_sys_traffic   m_ral_model;
      uvm_status_e      status;
      int               rdata;

      phase.raise_objection(this);
  
      `uvm_info(get_type_name(),"before making a call to    m_ral_model.cfg.timer[1].write inside test  ",UVM_MEDIUM)
     
     ral_sys_eon_h.pi_po_reg.write (status, 32'h3f);
     ral_sys_eon_h.pi_po_reg.write (status, 32'h3f);
     ral_sys_eon_h.pi_po_reg.write (status, 32'h3f);
     ral_sys_eon_h.pi_po_reg.write (status, 32'h3f);
    
    
     `uvm_info(get_type_name(), $sformatf("desired=0x%0h mirrored=0x%0h", ral_sys_eon_h.pi_po_reg.get(), ral_sys_eon_h.pi_po_reg.get_mirrored_value()), UVM_MEDIUM)
     
     `uvm_info(get_type_name(),"after making a call to    m_ral_model.cfg.timer[1].write inside test ",UVM_MEDIUM)
     
     
      //ral_sys_eon_h.pi_po_reg.read (status, rdata);
      phase.drop_objection(this);
   endtask
  
 
endclass

dave_59 · March 19, 2020, 4:33pm

In reply to santosh_dv:

You didn’t show reg_env which supposedly constructs m_ral_model. Normally one does

create()
build()
lock_model()

You do not put lock_model inside the reg_block.

santosh_dv · March 19, 2020, 4:58pm

In reply to dave_59:

Thanks for the response Dave_59.

1.As you suggested i have commented lock_model inside reg_block .
2.below i have added the code of register environment.

But still facing the same issue ,call to lock_model function is not returning at all.

//--------------register environment -------//
ifndef reg_env; define reg_env;
class reg_env extends uvm_env;

`uvm_component_utils (reg_env)

function new (string name=“reg_env”, uvm_component parent);
super.new (name, parent);
endfunction

ral_sys_eon m_ral_model; // Register Model
reg2spi_adapter m_reg2spi; // Convert Reg Tx ↔ Bus-type packets
uvm_reg_predictor #(spi_txn) m_spi2reg_predictor; // Map SPI tx to register in model
// Agent to drive/monitor transactions

virtual function void build_phase (uvm_phase phase);
super.build_phase (phase);

 `uvm_info(get_full_name(),"INSIDE REG ENV starting of BUILD PHASE",UVM_LOW)
 set_config_int( "*", "include_coverage", 0 );
 m_ral_model          = ral_sys_eon::type_id::create ("m_ral_model", this);
 m_reg2spi            = reg2spi_adapter :: type_id :: create ("m_reg2spi");
 m_spi2reg_predictor  = uvm_reg_predictor #(spi_txn) :: type_id :: create ("m_spi2reg_predictor", this);

  m_ral_model.build ();
 `uvm_info(get_type_name(),"calling the lock model  ",UVM_MEDIUM)
  m_ral_model.lock_model();
 `uvm_info(get_type_name(),"came out of lock model  ",UVM_MEDIUM)
 
 `uvm_info(get_full_name(),"INSIDE reg ENV ending of BUILD PHASE",UVM_LOW)

endfunction

virtual function void connect_phase (uvm_phase phase);
super.connect_phase (phase);
uvm_info(get_full_name(),"INSIDE reg ENV starting of connect PHASE",UVM_LOW) m_spi2reg_predictor.map = m_ral_model.default_map; m_spi2reg_predictor.adapter = m_reg2spi; uvm_info(get_full_name(),“INSIDE reg ENV ending of connect PHASE”,UVM_LOW)
endfunction
endclass
`endif

//-----------spi transaction class -----------//

ifndef spi_txn; define spi_txn;
class spi_txn extends uvm_sequence_item;

typedef enum bit {SPI_TXN_CMD_TYPE_WRITE=1’b0,

                 SPI_TXN_CMD_TYPE_READ=1'b1
					
                }spi_txn_cmd_type_e;

rand logic[7:0]addr;

rand logic[7:0]data;

rand spi_txn_cmd_type_e cmd_type;

function new(string name = “spi_txn”);

super.new(name);

endfunction

`uvm_object_utils_begin(spi_txn)

`uvm_field_int(addr,UVM_ALL_ON)

`uvm_field_array_int(data,UVM_ALL_ON)

`uvm_field_enum(spi_txn_cmd_type_e,cmd_type,UVM_ALL_ON)

`uvm_object_utils_end

function void post_randomize();

addr[7]=cmd_type;

endfunction

endclass