In reply to Shubhabrata:
In reply to ben@SystemVerilog.us:
…The updated form is working, right? I ran it and your solution on eda-playground and I didn’t notice any difference.
Correct, yours is the same as mine.
Actually, your solution seemed a little bit intricate to me. That’s why I tried to write the assertion with the techniques I have learned.
As you found out, there are many ways to approach an assertion. Your original question was that a certain event must occur within a range of cycles from n to m. if n and m were static, like 1 to 5, then you can use ##[1:5] var. However, SVA does not support dynamic ranges where n and m are defined in variables. This type of question came in very often. To solve this in a much easier way, I wrote a package, and YES, it is complex.
The count approach is definitely easier to understand and I too prefer it.
One more thing, the waveform you shared where your solution and my assumption can be observed clearly, over there I noticed one thing. In my case, ok2 is not exactly presented as ok signal. You also can notice that. Is that any kind of fault or something else?
It is something related to either the tools or the *$dumpfile(“dump.vcd”); $dumpvars;
*. I originally tested the code in eda and the OKs were delayed by one cycle; I could not explain it. Also, the displays of the count were odly duplicated. So I left my slick Pixelbook and tried my heavier laptop that has a full license of a simulator. The results there were as expected, and those are the ones I included in my last post.