Legal ways to specify the leading clock in SVA

SystemVerilog
,
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In reply to ben@SystemVerilog.us:

I think you might misunderstood my question, I am not saying forever is a procedural block. I know it’s not. 2017 LRM section 16.16 is about clock inference, and it doesn’t say anything about the illegality of forever_asrt statement in the following code

module test;

  bit clk;
  bit a,b;
  
  default clocking @(posedge clk); endclocking
  
  always #1 clk = ~clk;

  //----------------------//
  property forever_pp;
    a |-> b;
  endproperty
  
  //----------------------//
  initial begin
    forever @(posedge clk)begin
      forever_asrt: assert property(forever_pp);
    end
  end
        
  //----------------------//     
  initial begin
    #2 a=1; b=0;
    #20 $finish;
  end

So my question is which section in the LRM says using

assert property

is illegal in a looping statement?

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