Legal ways to specify the leading clock in SVA

SystemVerilog
,
6

In reply to ben@SystemVerilog.us:
Note that the following is also ILLEGAL even if you have a Leading Clocking Event (LCE)


initial begin
    forever @(posedge clk)begin
      forever_asrt: assert property( @(posedge clk) forever_pp);
    end
  end
 "assert property(@(posedge clk) forever_pp);"
  Procedural assertion ( i.e., assert, assume or cover property) is not 
  allowed in looping statement.  Only immediate assertions are allowed in this 
  context.

1800’2017: 9.2 Structured procedures All structured procedures in SystemVerilog are specified within one of the following constructs:
— initial procedure, denoted with the keyword initial (see 9.2.1 )
— always procedure, denoted with the keywords: • always (see 9.2.2.1 )
• always_comb (see 9.2.2.2 )
• always_latch (see 9.2.2.3 )
• always_ff (see 9.2.2.4 )
— final procedure, denoted with the keyword final (see 9.2.3)
— Task
— Function

Ben