Legal RD_PTR Values for WR_PTR

SystemVerilog
, ,
1

Hi All,

I am looking to cover legal Values of rd_ptr for any wr_ptr value for a FIFO Design.

Fifo_depth = 4, wr_ptr[1:0], rd_ptr[1:0].  

Case 1: wr_ptr > rd_ptr : 
        rd_ptr inside [ wr_ptr to 0 ] 
Case 2: wr_ptr < rd_ptr : 
        rd_ptr inside [ Fifo_Depth[3] to rd_ptr, (or) wr_ptr to 0 ] 

property valid_ptr_values; 
 @(posedge clk)  disable iff(!rst_n) 
   ----------------------
endproperty

Since using syntax “inside” you have to specify static range and not dynamic.

Anyone suggestion as to how to test this ?

Thanks